In a semiconductor integrated circuit used for a scan test of logic circuits, there is known a semiconductor integrated circuit configured to have an input terminal for data and another terminal for a test signal and to have a common data hold circuit connected to these input terminals. In such a semiconductor integrated circuit, there is known a semiconductor integrated circuit configured to have multiple data hold circuits connected to the data input terminal and a gate circuit that carries out a majority logic operation on the multiple data hold circuits (see Japanese Laid-Open Patent Application No. 2002-185309). With this structure, even if data is erroneously inverted in one of the data hold circuits, it is possible to output correct data by the gate circuit of the majority logic as long as the other data hold circuits hold correct data.
In the above-described semiconductor integrated circuit, in case where a soft error occurs in any of the data hold circuits, the output of the gate circuit for making the majority logic is floating, and data may be destroyed due to a leakage or the like. In order to prevent data from being destroyed, an additional data hold circuit may be connected to the output of the gate circuit. However, the use of the additional data hold circuit increases the circuit area.